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ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 1 of 49 1 - 888 - 824 - 4184 features form, fit, and function compatible with the intel a 8 0 44 / 8344 packaging options available: 40 pin plastic dual in - line package (pdip), 44 pin plastic leaded chip carrier (plcc) 8 - bit control unit 8 - bit arithmetic - logic unit with 16 - bit multiplicatio n and division 12 mhz clock four 8 - bit input / output ports two 16 - bit timer/counters serial interface unit with sdlc/hdlc compatibility 2.4 mbps maximum serial data rate two level priority interrupt system 5 interrupt sources internal clock prescaler and phase generator 192 bytes of read/write data memory space 64kb external program memory space 64kb external data memory space 4kb internal rom (ia8044 only) ia8044/ia8344 variants ia8044 4kb internal rom with r0117 version 2. 3 firmware, 192 byte intern al ram, 64kb external program and data space. ia8344 192 byte internal ram, 64kb external program and data space. the ia8044/ia8344 is a "plug - and - play" drop - in replacement for the original ic. innovasic produces replacement ics using its miles tm , or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than "emulation" while ensuring they are compatible with the original ic. miles tm captures the design of a clone so it can be produced even as silicon technology advances. miles tm also verifies the clone against the original ic so that even the "undocumented features" are duplicated. this data sheet documents all necessary engineering information about the ia8044/ia8344 including functional and i/o descriptions, electrical characteristics, and applicable timing. innov asic
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 2 of 49 1 - 888 - 824 - 4184 package pinout (6) p1.5 (1) p1.0 (2) p1.1 (3) p1.2 (4) p1.3 (5) p1.4 (7) (rts) p1.6 (8) (9) rst (10) (11) (12) (int0) p3.2 (13) (int1) p3.3 (14) 40 pin dip ia8x44 p0.7 (ad7) ea ale psen (20) vss (15) (sclk/t1) p3.5 (16) (wr) p3.6 (17) (rd) p3.7 (18) xtal2 (19) xtal1 (21) (22) (23) (24) p2.1 (a9) p2.0 (a8) (40) (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (t0) p3.4 p2.3 (a11) p2.2 (a10) p2.5 (a13) p2.4 (a12) p2.7 (a15) p2.6 (a14) p0.5 (ad5) p0.6 (ad6) p0.3 (ad3) p0.4 (ad4) p0.1 (ad1) p0.2 (ad2) vcc p0.0 (ad0) (cts) p1.7 (rxd) p3.0 (txd) p3.1 p1.3 p1.4 p3.6 p2.6 44 pin lcc ia8x44 (12) n.c. (7) p1.5 (8) p1.6 (9) p1.7 (10) rst/vpd (11) p3.0 (13) p3.1 (14) p3.2 (15) p3.3 (16) p3.4 (17) p3.5 p0.4 ale n.c. ea p0.6 p0.5 xtal2 p3.7 (6) (5) (4) (3) (2) (1) (44) (43) (42) p0.1 (41) p0.2 (40) p0.3 (34) (39) (38) (37) (36) (35) (33) (32) (31) (30) (29) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) vcc p0.0 p1.0 n.c. p1.2 p1.1 vss xtal1 p2.0 n.c. p2.2 p2.1 p2.4 p2.3 p2.5 p2.7 psen p0.7 description the ia8044/ia8344 is a form, fit and function compatible part to the intel 8x44 sdlc communications controller. t he ia8044/ia8344 is a fast single - chip 8 - bit microcontroller with an integrated sdlc/hdlc serial interface controller. the ia8044/ia8344 is a fully functional 8 - bit embedded controller that executes all asm51 instructions and has the same instruction set a s the intel 80c51. the ia8044/ia8344 can access the instructions from two types of program memory, serves software and hardware interrupts, provides an interface for serial communications and a timer system. the ia8044/ia8344 is fully compatible with the intel 8x44 series . the functional block diagram is shown below.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 3 of 49 1 - 888 - 824 - 4184 functional block diagram 192x8dual port ram c8051 cpu interrupts timers port 0 addr/data/io port 2 addr/data/io port 1 spcl func/io port 3 spcl func/io siu control address/data clock gen. & timing xtal reset memory control i/o for memory, siu, dma, interrupts, timers
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 4 of 49 1 - 888 - 824 - 4184 i/o characteristics the table below describes the i/o characteristics for each signal on the ic. the signal names correspond t o the signal names on the pinout diagrams provided . the table below provides the i/o description of the ia8044 and the ia8344. name type description rst i reset. this pin when held high for two machine cycles while the oscillator is running will cause th e chip to reset. ale o address latch enable. used to latch the address on the falling edge for external memory accesses. psen o program store enable. when low acts as an output enable for external program memory. ea i external access. when held low e a will cause the ia8044/ia8344 to fetch instructions from external memory. p0.7 ? p0.0 i/o port 0. 8 bit i/o port and low order multiplexed address/data byte for external accesses. p1.7 ? p1.0 i/o port 1. 8 - bit i/o port. two bits have alternate functi ons, p1.6 (rts) and p1.7 (cts). p2.7 ? p2.0 i/o port 2. 8 - bit i/o port. it also functions as the high order address byte during external accesses. p3.7 ? p3.0 i/o port 3. 8 - bit i/o port. port 3 bits also have alternate functions as described below. p 3.0 ? rxd. receive data input for siu or direction control for p3.1 dependent upon datalink configuration. p3.1 ? txd. transmit data output for siu or data input/output dependent upon datalink configuration. also enables diagnostic mode when cleared. p3 .2 ? int0. interrupt 0 input or gate control input for counter 0. p3.3 ? int1. interrupt 1 input or gate control input for counter 1. p3.4 ? t0. input to counter 0. p3.5 ? sclk/t1. sclk input to siu or input to counter 1. p3.6 ? wr. external memory wr ite signal. p3.7 ? rd. external memory read signal. xtal1 i crystal input 1. connect to vss when external clock is used on xtal2. may be connected to a crystal (with xtal2), or may be driven directly with a clock source (xtal2 not connected). xtal2 o c rystal input 2. may be connected to a crystal (with xtal1), or may be driven directly with an inverted clock source (xtal1 tied to ground). vss p ground. vcc p +5v power.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 5 of 49 1 - 888 - 824 - 4184 memory organization program memory program memory includes interrupt and reset vectors. the interrupt vectors are spaced at 8 - byte intervals, starting from 0003h for external interrupt 0. reset vectors these locations may be used for program code, if the corresponding interrupts are not used (disabled). the program memory space is 64k, from 0000h to ffffh. the lowest 4k of program code (0000h to 0fffh) can be fetched from external o r internal program memory. this selection is made by strapping pin ?ea? (external address) to gnd or vcc. if during reset, ?ea? is held low, all the program code is fetched from external memory. if, during reset, ?ea? is held high, the lowest 4k of progra m code (0000h to 0fffh) is fetched from internal memory (rom). program memory addresses above 4k (0fffh) will cause the program code to be fetched from external memory regardless of the setting of ?ea?. data memory external data memory the ia8044/ia8344 microcontroller core incorporates the harvard architecture, with separate code and data spaces. the code from external memory is fetched by ?psen? strobe, while data is read from ram by bit 7 of p3 (read strobe) and written to ram by bit 6 of p3 (write st robe). the external data memory space is active only by addressing through use of the movx instruction and the 16 - bit data pointer register (dptr). a smaller subset of external data memory (8 bit addressing) may be accessed by using the movx instruction w ith register indexed addressing. internal data memory the internal data memory address is always 1 byte wide. the memory space is 192 bytes large (00h to bfh), and can be accessed by either direct or indirect addressing. the special function registers occ upy the upper 128 bytes. this sfr area is available only by direct addressing. internal memory that overlaps the sfr address space is only accessible by indirect addressing. location service 0003h external interrupt 0 000bh timer 0 overflow 0013h external interrupt 1 001bh timer 1 overflow 0023 h siu interrupt
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 6 of 49 1 - 888 - 824 - 4184 internal memory 8044 internal data memory addresses 00h to ffh 80h ffh 80h bfh indirect addressing ram 00h 07h 08h 17h 18h 1fh 20h 2fh 30h 7fh 10h 0fh register bank 0 register bank 1 register bank 2 register bank 3 bit addressable memory internal data ram direct addressing special function registers addressable bits in sfrs (128 bits)
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 7 of 49 1 - 888 - 824 - 4184 bit addressable memory both the in ternal ram and the special function registers have locations that are bit addressable in addition to the byte addressable locations. sfr bit addressable locations byte address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register f0h f7h f6h f5h f4h f 3h f2h f1h f0h b e0h e7h e6h e5h e4h e3h e2h e1h e0h acc d8h dfh deh ddh dch dbh dah d9h d8h nsnr d0h d7h d6h d5h d4h d3h d2h d1h d0h psw c8h cfh ceh cdh cch cbh cah c9h c8h sts b8h - - - bch bbh bah b9h b8h ip b0h b7h b6h b5h b4h b3h b2h b1h b0h p3 a8h afh - - ach abh aah a9h a8h ie a0h a7h a6h a5h a4h a3h a2h a1h a0h p2 90h 97h 96h 95h 94h 93h 92h 91h 90h p1 88h 8fh 8eh 8dh 8ch 8bh 8ah 89h 88h tcon 80h 87h 86h 85h 84h 83h 82h 81h 80h p0 internal ram bit addressable locations byte address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 30h - bfh upper internal ram locations 2fh 7fh 7eh 7dh 7ch 7bh 7ah 79h 78h 2eh 77h 76h 75h 74h 73h 72h 71h 70h 2dh 6fh 6eh 6dh 6ch 6bh 6ah 69h 68h 2ch 67h 66h 65h 64h 63h 62h 61h 60h 2bh 5fh 5eh 5dh 5ch 5bh 5a h 59h 58h 2ah 57h 56h 55h 54h 53h 52h 51h 50h 29h 4fh 4eh 4dh 4ch 4bh 4ah 49h 48h 28h 47h 46h 45h 44h 43h 42h 41h 40h 27h 3fh 3eh 3dh 3ch 3bh 3ah 39h 38h 26h 37h 36h 35h 34h 33h 32h 31h 30h 25h 2fh 2eh 2dh 2ch 2bh 2ah 29h 28h 24h 27h 26h 25h 24h 23h 22h 21h 20h 23h 1fh 1eh 1dh 1ch 1bh 1ah 19h 18h 22h 17h 16h 15h 14h 13h 12h 11h 10h 21h 0fh 0eh 0dh 0ch 0bh 0ah 09h 08h 20h 07h 06h 05h 04h 03h 02h 01h 00h 18h - 1fh register bank 3 10h - 17h register bank 2 08h - 0fh register bank 1 00h - 07h register ba nk 0
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 8 of 49 1 - 888 - 824 - 4184 instruction set the 8x44 architecture and instruction set are identical to the 8051?s. the following tables give a survey of the instruction set of the ia8044/ia8344 microcontroller core. arithmetic operations mnemonic description byte cycle add a,rn add register to accumulator 1 1 add a, direct add direct byte to accumulator 2 1 add a,@ri add indirect ram to accumulator 1 1 add a,#data add immediate data to accumulator 2 1 addc a,rn add register to accumulator with carry flag 1 1 addc a,direct add direct byte to a with carry flag 2 1 addc a,@ri add indirect ram to a with carry flag 1 1 addc a,#data add immediate data to a with carry flag 2 1 subb a,rn subtract register from a with borrow 1 1 subb a,direct subtract di rect byte from a with borrow 2 1 subb a,@ri subtract indirect ram from a with borrow 1 1 subb a,#data subtract immediate data from a with borrow 2 1 inc a increment accumulator 1 1 inc rn increment register 1 1 inc direct increment direct by te 2 1 inc @ ri increment indirect ram 1 1 dec a decrement accumulator 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 1 dec @ri decrement indirect ram 1 1 inc dptr increment data pointer 1 2 mul a,b multiply a and b 1 4 div a,b divide a by b 1 4 da a decimal adjust accumulator 1 1
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 9 of 49 1 - 888 - 824 - 4184 logic operations mnemonic description byte cycle anl a,rn and register to accumulator 1 1 anl a,direct and direct byte to accumulator 2 1 anl a,@ri and indirect ram to accumulator 1 1 anl a,#data and immediate data to accumulator 2 1 anl direct,a and accumulator to direct byte 2 1 anl direct,#data and immediate data to direct byte 3 2 orl a,rn or register to accumulator 1 1 orl a,direct or direct byte to acc umulator 2 1 orl a,@ri or indirect ram to accumulator 1 1 orl a,#data or immediate data to accumulator 2 1 orl direct,a or accumulator to direct byte 2 1 orl direct,#data or immediate data to direct byte 3 2 xrl a,rn exclusive or register to a ccumulator 1 1 xrl a,direct exclusive or direct byte to accumulator 2 1 xrl a,@ri exclusive or indirect ram to accumulator 1 1 xrl a,#data exclusive or immediate data to accumulator 2 1 xrl direct,a exclusive or accumulator to direct byte 2 1 x rl direct,#data exclusive or immediate data to direct byte 3 2 clr a clear accumulator 1 1 cpl a complement accumulator 1 1 rl a rotate accumulator left 1 1 rlc a rotate accumulator left through carry 1 1 rr a rotate accumulator right 1 1 rrc a rotate accumulator right through carry 1 1 swap a swap nibbles within the accumulator 1 1
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 10 of 49 1 - 888 - 824 - 4184 data transfer mnemonic description byte cycle mov a,rn move register to accumulator 1 1 mov a,direct move direct byte to accumulator 2 1 mov a,@ri move indirect ram to accumulator 1 1 mov a,#data move immediate data to accumulator 2 1 mov rn,a move accumulator to register 1 1 mov rn,direct move direct byte to register 2 2 mov rn,#data move immediate data to register 2 1 mov direc t,a move accumulator to direct byte 2 1 mov direct,rn move register to direct byte 2 2 mov direct,direct move direct byte to direct byte 3 2 mov direct,@ri move indirect ram to direct byte 2 2 mov direct,#data move immediate data to direct byte 3 2 mov @ri,a move accumulator to indirect ram 1 1 mov @ri,direct move direct byte to indirect ram 2 2 mov @ ri, #data move immediate data to indirect ram 2 1 mov dptr, #data16 load data pointer with a 16 - bit constant 3 2 movc a,@a + dptr m ove code byte relative to dptr to accumulator 1 2 movc a,@a + pc move code byte relative to pc to accumulator 1 2 movx a,@ri move external ram (8 - bit addr.) to a 1 2 movx a,@dptr move external ram (16 - bit addr.) to a 1 2 movx @ri,a move a to exte rnal ram (8 - bit addr.) 1 2 movx @dptr,a move a to external ram (16 - bit addr.) 1 2 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a,rn exchange register with accumulator 1 1 xch a,direct exchange direc t byte with accumulator 2 1 xch a,@ri exchange indirect ram with accumulator 1 1 xchd x,@ ri exchange low - order nibble indir. ram with a 1 1
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 11 of 49 1 - 888 - 824 - 4184 boolean manipulation mnemonic description byte cycle clr c clear carry flag 1 1 clr bit clear dire ct bit 2 1 setb c set carry flag 1 1 setb bit set direct bit 2 1 cpl c complement carry flag 1 1 cpl bit complement direct bit 2 1 anl c,bit and direct bit to carry flag 2 2 anl c,bit and complement of direct bit to carry 2 2 orl c,bit o r direct bit to carry flag 2 2 orl c,bit or complement of direct bit to carry 2 2 mov c,bit move direct bit to carry flag 2 1 mov bit,c move carry flag to direct bit 2 2 program branches mnemonic description byte cycle acall addr11 absolute subroutine call 2 2 lcall addr16 long subroutine call 3 2 ret return from subroutine 1 2 reti return from interrupt 1 2 ajmp addr11 absolute jump 2 2 ljmp addr16 long jump 3 2 sjmp rel short jump (relative addr.) 2 2 jmp @a + dptr jump indirect relative to the dptr 1 2 jz rel jump if accumulator is zero 2 2 jnz rel jump if accumulator is not zero 2 2 jc rel jump if carry flag is set 2 2 jnc rel jump if carry flag is not set 2 2 jb bit,rel jump if direct bit is set 3 2 jnb b it,rel jump if direct bit is not set 3 2 jbc bit,rel jump if direct bit is set and clear bit 3 2 cjne a,direct,rel compare direct byte to a and jump if not equal 3 2 cjne a,#data,rel compare immediate to a and jump if not equal 3 2 cjne rn,#data rel compare immed. to reg. and jump if not equal 3 2 cjne @ri,#data,rel compare immed. to ind. and jump if not equal 3 2 djnz rn,rel decrement register and jump if not zero 2 2 djnz direct,rel decrement direct byte and jump if not zero 3 2 nop no operation 1 1
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 12 of 49 1 - 888 - 824 - 4184 special function registers the ia8044/ia8344 contains the following special function registers: symbol register description byte address(hex) bit addresses (hex) (msb - lsb) acc accumulator e0h e7h ? e0h b b register f0h f7h ? f0h psw program status word d0h d7h ? d0h sp stack pointer 81h - dph data pointer high byte 82h - dpl data pointer low byte 83h - p0 port 0 80h 87h ? 80h p1 port 1 90h 97h ? 90h p2 port 2 a0h a7h ? a0h p3 port 3 b0h b7h ? b0h ip interrupt pri ority b8h bch ? b8h ie interrupt enable a8h afh,ach ? a8h tmod timer/counter mode 89h - tcon timer/counter control 88h 8fh ? 88h th0 timer/counter 0 high byte 8ch - tl0 timer/counter 0 low byte 8ah - th1 timer/counter 1 high byte 8dh - tl1 timer/ counter 1 low byte 8bh - smd serial mode c9h - sts siu status and command c8h cfh ? c8h nsnr siu send/receive count d8h dfh ? d8h stad siu station address ceh - tbs transmit buffer start address dch - tbl transmit buffer length dbh - tcb transmit control byte dah - rbs receive buffer start address cch - rbl receive buffer length cbh - rfl receive field length cdh - rcb receive control byte cah - dma cnt dma count cfh - fifo fifo contents (3 bytes) df,de,ddh - siust siu state counter d9h -
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 13 of 49 1 - 888 - 824 - 4184 ports ports p0, p1, p2 and p3 are special function registers. the contents of the sfr can be observed on corresponding pins on the chip. writing a ?1? to any of the ports causes the corresponding pin to be at high level (vcc), and writing a ?0? causes the corresponding pin to be held at low level (gnd). all four ports on the chip are bi - directional. each of them consists of a latch (sfr p0 to p3), an output driver, and an input buffer, so the cpu can output or read data through any of these ports if they are not used for alternate purposes. ports p0, p1, p2 and p3 can perform some alternate functions. ports p0 and p2 are used to access external memory. in this case, port ?p0? outputs the multiplexed lower 8 bits of address with ?ale? strobe high and then reads/writes 8 bits of data. port p2 outputs the higher 8 bits of address. keeping ?ea? pin low (tied to gnd) activates this alternate function for ports p0 and p2. port p3 and p1 can perform some alternate functions. the pins of port p3 are multifunction al. they can perform additional functions as described below. pin symbol function p3.0 rxd, i/o in point - to - point or multipoint configurations (smd.3 = 0) this pin is i/o and signals the direction of data flow on data (p3.1). in loop mode (smd.3 = 1) a nd diagnostic mode this pin is rxd, receive data input. p3.1 txd, data in point to point or multipoint configurations (smd.3 = 0) this pin is data and is the transmit/receive data pin. in loop mode (smd.3 = 1) this pin is the transmit data, txd, pin. w riting a ?0? to this port buffer bit enables the diagnostic mode. p3.2 int0 external interrupt 0 input. also gate control input for counter 0. p3.3 int1 external interrupt 1 input. also gate control input for counter 1. p3.4 t0 timer/counter 0 external input. setting the appropriate bits in the special function registers tcon and tmod activates this function. p3.5 t1, sclk timer/counter 1 external input. setting the appropriate bits in the special function registers tcon and tmod activates t his function. . can also function as the external clock source for the siu. p3.6 wr external data memory write strobe, active low. this function is activated by a cpu write access to external data memory (i.e. movx @dptr, a).
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 14 of 49 1 - 888 - 824 - 4184 p3.7 rd external da ta memory read strobe, active low. this function is activated by a cpu read access from external data memory (i.e. movx a, @dptr). p1.6 rts request to send output, active low. p1.7 cts clear to send input, active low. port registers port 0 (p0): gener al purpose, 8 bit, i/o port and multiplexed low order address and data bus with open - drain output buffers. p0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 port 1 (p1): general purpose, 8 bit, i/o port with pullups and auxiliary fun ctions. p1 bit: 7 6 5 4 3 2 1 0 rts/p1.7 cts/p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p1.0 - p1.1 - p1.2 - p1.3 - p1.4 - p1.5 - p1.6 rts request to send output. p1.7 cts clear to send input. port 2 (p2): general purpose, 8 bit, i /o port with pullups and high order address bus. p2 bit: 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 15 of 49 1 - 888 - 824 - 4184 port 3 (p3): general purpose, 8 - bit i/o port with pullups and auxiliary functions. bits on this port also functions as the siu data tran smit/receive i/o, external interrupt inputs, timer inputs and the read and write strobes for external memory accesses. p3 bit: 7 6 5 4 3 2 1 0 rd wr t1 t0 int1 int0 txd rxd p3.0 rxd serial input pin. p3.1 txd serial output pin. p3.2 int0 extern al interrupt 0. p3.3 int1 external interrupt 1. p3.4 t0 timer/counter 0 external input. p3.5 t1 timer/counter 1 external input. p3.6 wr external data memory write strobe, active low. p3.7 rd external data memory read strobe, active low.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 16 of 49 1 - 888 - 824 - 4184 tim ers/counters timers 0 and 1 the ia8x44 has two 16 - bit timer/counter registers: timer 0 and timer 1. both can be configured for counter or timer operations. in timer mode, the register is incremented every machine cycle, which means that it counts up afte r every 12 oscillator periods. in counter mode, the register is incremented when the falling edge is observed at the corresponding input pin t0 or t1. since it takes 2 machine cycles to recognize a 1 - to - 0 event, the maximum input count rate is 1/24 of the oscillator frequency. there are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle (12 clock periods). four operating modes can be selected for timer 0 and timer 1. two special function registers (tmod and tcon) are used to select the appropriate mode. mode 0 in mode 0 the timers operate as an 8 - bit timer (th0/1) with a divide by 32 bit prescalar (tl0/1). mode 0 uses all 8 bits of th0/1 and the lower 5 bits of t l0/1. the upper 3 bits of tl0/1 are unknowns. setting tr0/1 does not reset the registers th0/1 and tl0/1. as the timer rolls over from all 1?s to all 0?s it will set the interrupt flag tf0/1. mode 1 mode 1 is the same as mode 0 except that all 8 bits of tl0/1 are used instead of just the lower 5 bits. mode 2 mode 2 configures tl0/1 as an 8 - bit counter with automatic reload from the contents of th0/1. overflow of tl0/1 causes the interrupt tf0/1 to be set and the reload to occur. the contents of th0/ 1 are not affected by the reload. mode 3 mode 3 creates two separate 8 bit counters from tl0 and th0. tl0 uses the timer 0 mode bits from tmod, tmod .0 through tmod.3. th0 is a timer only (not a counter) and uses timer 1?s control bits, tr1 and tf1 for operation. timer 1 can still be used if an interrupt is not required by switching it in and out of its own mode 3. with tmod.4 and tmod.5 both high timer 1 will stop and hold its count. timer mode (tmod): the timer mode register contains bits that selec t the mode that the timers are to be operated in. the lower nibble controls timer 0 and the upper nibble controls timer 1. tmod bit: 7 6 5 4 3 2 1 0 gate c/t m1 m0 gate c/t m1 m0 tmod.0 m0 timer 0 mode selector bit.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 17 of 49 1 - 888 - 824 - 4184 tmod.1 m1 timer 0 mode selecto r bit. tmod.2 c/t c/t selects timer0 or counter0 operation. when set to 1, the counter operation is performed, when cleared to 0, the register will function as a timer. tmod.3 gate if set, enables external gate control for counter/timer0 (pin int0/ fo r counter 0). when int0/ is high, and tr0 bit is set (see tcon register), the counter is incremented every falling edge on t0 input pin. tmod.4 m0 timer 1 mode selector bit. tmod.5 m1 timer 1 mode selector bit. tmod.6 c/t c/t selects timer1 or co unter1 operation. when set to 1, the counter operation is performed, when cleared to 0, the register will function as a timer. tmod.7 gate if set, enables external gate control for counter/timer1 (pin int1/ for counter 1). when int1/ is high, and tr1 bi t is set (see tcon register), the counter is incremented every falling edge on t1 input pin.. timer mode select bits m1 m0 operating mode 0 0 0 13 bit timer 0 1 1 16 bit timer/counter 1 0 2 8 bit auto - reload timer/counter 1 1 3 timer0 ? tl0 is a stand ard 8 - bit timer/counter controlled by timer 0 control bits. th0 is an 8 - bit timer function only, controlled by timer 1 control bits. 1 1 3 timer/counter1 stopped and holds its count. can be used to start/stop timer 1 when timer 0 is in mode 3. ti mer control (tcon): the timer control register provides control bits that start and stop the counters. it also contains bits to select the type of external interrupt desired, edge or level. additionally tcon contains status bits showing when a timer over flows and when an interrupt edge has been detected. tcon bit: 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tcon.0 it0 interrupt 0 type control bit. selects falling edge or low level on input pin to cause interrupt. tcon.1 ie0 interrupt 0 edge f lag. set by hardware, when falling edge on external pin int1/ is observed. cleared when interrupt is processed. tcon.2 it1 interrupt 1 type control bit. selects falling edge or low level on input pin to cause interrupt.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 18 of 49 1 - 888 - 824 - 4184 tcon.3 ie1 interrupt 1 edge flag . set by hardware, when falling edge on external pin int1/ is observed cleared when interrupt is processed. tcon.4 tr0 timer 0 run control bit. if cleared, timer 0 stops. tcon.5 tf0 timer 0 overflow flag set by hardware when timer 0 overflows. this fl ag should be cleared by software. tcon.6 tr1 timer 1 run control bit. if cleared, timer 1 stops. in mode 3 this bit controls th0. tcon.7 tf1 timer 1 overflow flag set by hardware when timer 1 overflows. this flag should be cleared by software.. in mode 3 this bit is controlled by th0. timer 0 high byte (th0): high order byte of timer/counter0. th0 bit: 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 timer 0 low byte (tl0): low order byte of timer/counter0. tl0 bi t: 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 timer 1 high byte (th1): high order byte of timer/counter1. th1 bit: 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 timer 1 low byte (tl1): low order byte o f timer/counter1. tl1 bit: 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 19 of 49 1 - 888 - 824 - 4184 timers/counters configuration timer 0 mode 0 osc tlo (5 bits ) th0 (8 bits) tf0 =1 & 1 3 interrupt p3.4/t0 gate p3.2/int0 tr0 control 1 t c/ = 0 t c/ = 12 ? timer 0 mode 1
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 20 of 49 1 - 888 - 824 - 4184 timer 0 mode 2 osc tlo (8 bits ) th0 (8 bits) tf0 =1 & 1 3 interrupt p3.4/t0 gate p3.2/int0 tr0 control 1 t c/ = 0 t c/ = 12 ? reload timer 0 mode 3 osc tlo (8 bits ) th0 (8 bits) tf0 =1 & 1 3 interrupt p3.4/t0 gate p3.2/int0 tr0 control 1 t c/ = 0 t c/ = 12 ? tf1 1/12 f osc 1/12 f osc tr1 control interrupt
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 21 of 49 1 - 888 - 824 - 4184 reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. the cpu responds by generating an internal reset, whic h is executed during the second cycle in which rst is high. the internal reset sequence affects all sfrs as shown below. the internal reset sequence does not affect the contents of internal ram. reset values register reset value pc 0000h acc 0000000 0b b 00000000b psw 00000000b sp 00000111b dptr 0000h p0 ? p3 11111111b ip xxx00000b ie 0xx00000b tmod 00000000b tcon 00000000b th0 00000000b tl0 00000000b th1 00000000b tl1 00000000b smd 00000000b sts 00000000b nsnr 00000000b stad xxxxxxxxb tbs xxxxxxxxb tbl xxxxxxxxb tcb xxxxxxxxb rbs xxxxxxxxb rbl xxxxxxxxb rfl xxxxxxxxb rcb xxxxxxxxb dma cnt 00000000b fifo1 00000000b fifo2 00000000b fifo3 00000000b siust 00000001b
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 22 of 49 1 - 888 - 824 - 4184 general cpu registers accumulator (acc): acc is the accumulator register. most instructions use the accumulator to hold the operand. the mnemonics for accumulator - specific instructions refer to accumulator as a, not acc. acc bit: 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 b register (b): the b register is used during multiply and divide instructions. it can also be used as a scratch - pad register to hold temporary data. b bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 program status word (psw): contains cpu st atus flags, register select bits and user flags. psw bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov - p psw.0 p parity flag, affected by hardware to indicate odd / even number of ?one? bits in the accumulator, i.e. even parity. psw.1 - user defined flag . psw.2 ov overflow flag. psw.3 rs0 register bank select control bit 0, used to select working register bank. psw.4 rs1 register bank select control bit 1, used to select working register bank. psw.5 f0 general purpose flag 0 available for user. p sw.6 ac auxiliary carry flag for carry out of or into bit 3. psw.7 cy carry flag for carry out of or into bit 7.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 23 of 49 1 - 888 - 824 - 4184 the state of bits rs1, rs0 selects the working registers bank as follows: rs1/0 bank selected location 00 bank 0 (00h ? 07h) 01 bank 1 (08h ? 0fh) 10 bank 2 (10h ? 17h) 11 bank 3 (18h ? 1fh) stack pointer (sp): the stack pointer is a 1 - byte register initialized to 07h after reset. this register is incremented before push and call instructions, causing the stack to begin at loc ation 08h. the stack pointer points to a location in internal ram. sp bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 data pointer (dptr): the data pointer (dptr) is 2 bytes wide. the lower part is dpl, and the highest is dph. it ca n be loaded as 2 byte register (mov dptr,#data16) or as two registers (ea. mov dpl,#data8). it is generally used to access external code or data space (ea. movc a,@a+dptr or mov a,@dptr respectively). dph bit: 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph .3 dph.2 dph.1 dph.0 dpl bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 24 of 49 1 - 888 - 824 - 4184 interrupts the ia8044/ia8344 provides 5 interrupt sources. there are 2 external interrupts accessible through pins int0 and int1, edge or level sensi tive (falling edge or low level). there are, also, internal interrupts associated with timer 0 and timer 1, and an internal interrupt from the siu. external interrupts the choice between external interrupt level or transition activity is made by setting i t1 and it0 bits in the special function register tcon. when the interrupt event happens, a corresponding interrupt control bit is set (it0 or it1). this control bit triggers an interrupt if the appropriate interrupt bit is enabled. when the interrupt servi ce routine is vectored, the corresponding control bit (it0 or it1) is cleared provided that the edge triggered mode was selected. if level mode is active, the external requesting source controls flags it0 or it1 by the logic level on pins int0 or int1 (0 o r 1). timer0 and timer 1 interrupts timer 0 and 1 interrupts are generated by tf0 and tf1 flags, which are set by the rollover of timer 0 and 1, respectively. when an interrupt is generated, the flag that caused this interrupt is cleared by the hardware , if the cpu accessed the corresponding interrupt service vector. this can be done only if this interrupt is enabled in the ie register. serial interface unit interrupt the siu generates an interrupt when a frame is received or transmitted. no interrupts are generated for a received frame with errors. interrupt priority level structure there are two priority levels in the ia8044/ia8344, and any interrupt can be individually programmed to a high or low priority level. modifying the appropriate bits in the special function register ip can accomplish this. a low priority interrupt service routine will be interrupted by a high priority interrupt. however, the high priority interrupt can not be interrupted. if two interrupts of the same priority level occur, an internal polling sequence determines which of them will be processed first. this polling sequence is a second priority structure defined as follows: ie0 1 ? highest tf0 2 ie1 3 tf1 4 siu ? lowest
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 25 of 49 1 - 888 - 824 - 4184 interrupt handling the interrupt flags are sampled du ring each machine cycle. the samples are polled during the next machine cycle. if an interrupt flag is captured, the interrupt system will generate an lcall instruction to the appropriate service routine, provided that this is not disabled by the following conditions: 1. an interrupt of the same or higher priority is processed 2. the current machine cycle is not the last cycle of the instruction (the instruction can not be interrupted). 3. the instruction in progress is reti or any write to ie or ip registe rs. note that if an interrupt is disabled and the interrupt flag is cleared before the blocking condition is removed, no interrupt will be generated, since the polling cycle will not sample any active interrupt condition. in other words, the interrupt cond ition is not remembered. every polling cycle is new. interrupt priority register (ip): this register sets the interrupt priority to high or low for each interrupt. when the bit is set it selects high priority. within each level the interrupts are priori tized as follows: external interrupt 0 timer/counter 0 external interrupt 1 timer/counter 1 siu. an interrupt process routine cannot be interrupted by an interrupt of lesser or equal priority. ip bit: 7 6 5 4 3 2 1 0 - - - ps pt1 px1 pt0 px0 ip.0 p x0 external interrupt 0 interrupt priority bit. ip.1 pt0 timer 0. interrupt priority bit. ip.2 px1 external interrupt 1. interrupt priority bit. ip.3 pt1 timer 1 interrupt priority bit. ip.4 ps siu interrupt priority bit. ip.5 - ip.6 - ip.7 -
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 26 of 49 1 - 888 - 824 - 4184 interrupt enable register (ie): contains the global interrupt enable bit and individual interrupt enable bits. setting a bit enables the corresponding interrupt. ie bit: 7 6 5 4 3 2 1 0 ea - - es et1 ex1 et0 ex0 pcon.0 ex0 external interru pt 0 interrupt enable bit. pcon.1 et0 timer 0. interrupt enable bit. pcon.2 ex1 external interrupt 1. interrupt enable bit. pcon.3 et1 timer 1 interrupt enable bit. pcon.4 es siu interrupt enable bit. pcon.5 - pcon.6 - pcon.7 ea enable all interrupts bit.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 27 of 49 1 - 888 - 824 - 4184 siu ? serial interface unit the siu is a serial interface customized to support sdlc/hdlc protocol. as such it supports zero bit insertion/deletion, flags automatic access recognition and a 16 bit crc. the siu has two modes of operatio n auto and flexible. the auto mode uses a subset of the sdlc protocol implemented in hardware. this frees the cpu from having to respond to every frame but limits the frame types. in the flexible mode every frame is under cpu control and therefore more options are available. the siu is controlled by and communicates to the cpu by using several special function registers (sfrs). data transmitted by or received by the siu is stored in the 192 byte internal ram in blocks referred to as the transmit and re ceive buffers. the siu can support operation in one of three serial data link configurations: 1) half - duplex, point - to - point, 2) half - duplex, multipoint, 3) loop mode. siu special function registers the cpu controls the siu and receives status from t he siu via eleven special function registers. the serial interface unit control registers are detailed below: serial mode register (smd): the serial mode register sets the operational mode of the siu. the cpu can read and write smd. the siu can read s md. to prevent conflicts between cpu and siu accesses to smd the cpu should write smd only when rts and rbe bits in the sts register are both zero. smd is normally only accessed during initialization. this register is byte addressable. smd bit: 7 6 5 4 3 2 1 0 scm2 scm1 scm0 nrzi loop pfs nb nfcs smd.0 nfcs when set selects no fcs field contained in the sdlc frame. smd.1 nb non - buffered mode. no control field contained in sdlc frame. smd.2 pfs pre - frame sync mode. when set causes two bytes to be transmitted before the first flag of the frame for dpll synchronization. if nrzi is set 00h is transmitted otherwise 55h. this ensures that 16 transitions are sent before the opening flag. smd.3 loop when set selects loop configuration else point - to - point mode. smd.4 nrzi when set selects nrzi encoding otherwise nrz. smd.5 scm0 select clock mode - bit 0. smd.6 scm1 select clock mode - bit 1. smd.7 scm2 select clock mode - bit 2.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 28 of 49 1 - 888 - 824 - 4184 smd select clock mode bits scm 2 1 0 clock mode data rate (bits/se c)* 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 externally clocked undefined self clocked, timer overflow undefined self clocked, external 16x self clocked, external 32x self clocked, internal fixed self clocked, internal fixed 0 ? 2.4m** 244 ? 62.5k 0 ? 375k 0 ? 187.5k 375k 187.5k * based on a12 mhz crystal frequency ** 0 ? 1m bps in loop configuration status/command register (sts): the status/command register provides siu control from and status to the cpu. the siu can read the sts and can write certain bits in the sts. the cpu can read and write the sts. accessing the sts by the cpu via 2 cycle instructions (jbc bit,rel and mov bit,c) should not be used. sts is bit addressable. sts bit: 7 6 5 4 3 2 1 0 tbf rbe rts si bov o pb am rbp sts.0 rbp receive buffer protect. when set prevents writing of data into the receive buffer. causes rnr response instead of rr in auto mode. sts.1 am auto mode. dual purpose bit depending upon the setting of bit nb (smd.1). if nb is cleared, am selects the auto mode when set, flexible mode when clear. if nb is set, am selects the addressed mode when set and the non - addressed mode when clear. the siu can clear am. sts.2 opb optional poll bit. when set the siu will auto respond to an optional poll (up with p=0). the siu can set or clear the opb. sts.3 bov receive buffer overrun. the siu can set or clear bov. sts.4 si siu interrupt. this bit is set by the siu and should be cleared by the cpu before returning from the interru pt routine. sts.5 rts request to send. this bit is set when the siu is ready to transmit or is transmitting. may be written by the siu in auto mode. rts is only applied to the external pin in non - loop mode. can be thought of as a transmit enable. no te: rts signal at the pin (p1.6) is the inverted version of this bit.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 29 of 49 1 - 888 - 824 - 4184 sts.6 rbe receive buffer empty. rbe is set by the cpu when it is ready to receive a frame or has just read the buffer. rbe is cleared by the siu when a frame has been received. c an be thought of as a receive enable. sts.7 tbf transmit buffer full. tbf is set by the cpu to indicate that the transmit buffer is ready and tbf is cleared by the siu. send/receive count register (nsnr): the nsnr contains both the transmit and recei ve sequence numbers in addition to the tally error indications. the cpu can read and write the sts. accessing the sts by the cpu via 2 cycle instructions (jbc bit,rel and mov bit,c) should not be used. the siu can read and write the nsnr. the ns and nr counters are not used in non - auto mode. nsnr is bit addressable. nsnr bit: 7 6 5 4 3 2 1 0 ns2 ns1 ns0 ses nr2 nr1 nr0 ser nsnr.0 ser sequence error receive. ns (p) ? nr (s). nsnr.1 nr0 receive sequence counter, bit 0. nsnr.2 nr1 receive sequence counter, bit 1. nsnr.3 nr2 receive sequence counter, bit 2. nsnr.4 ses sequence error send. nr (p) ? ns (s) and nr (p) ? ns (s) + 1. nsnr.5 ns0 send sequence counter, bit 0. nsnr.6 ns1 send sequence counter, bit 1. nsnr.7 ns2 send sequence counter, bit 2. station address register (stad): the stad contains the station address (node address) of the chip. the cpu can read or write stad but should access stad only when rts = 0 and rbe = 0. normally stad is accessed only during initialization. stad is byte addressable. stad bit: 7 6 5 4 3 2 1 0 stad.7 stad.6 stad.5 stad.4 stad.3 stad.2 stad.1 stad.0
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 30 of 49 1 - 888 - 824 - 4184 transmit buf fer start address register (tbs): the tbs contains the address in internal ram where the frame (starting with the i - field) to be transmitted is stored. the cpu should access tbs only when the siu is not transmitting a frame, tbf = 0. tbs is byte addressa ble. tbs bit: 7 6 5 4 3 2 1 0 tbs.7 tbs.6 tbs.5 tbs.4 tbs.3 tbs.2 tbs.1 tbs.0 transmit buffer length register (tbl): the tbl contains the length, in number of bytes, of the i - field to be transmitted. tbl = 0 is valid (no i - field). the cpu should a ccess tbl only when the siu is not transmitting a frame, tbf = 0. the transmit buffer will not wrap around after address 191 (bfh). a buffer end is automatically generated when address 191 is reached. tbl is byte addressable. tbl bit: 7 6 5 4 3 2 1 0 tbl.7 tbl.6 tbl.5 tbl.4 tbl.3 tbl.2 tbl.1 tbl.0 transmit control byte register (tcb): the tcb contains the byte to be placed in the control field of the transmitted frame during non - auto mode transmission. the cpu should access tcb only when the siu is not transmitting a frame, tbf = 0. tcb is byte addressable. tcb bit: 7 6 5 4 3 2 1 0 tcb.7 tcb.6 tcb.5 tcb.4 tcb.3 tcb.2 tcb.1 tcb.0 receive buffer start address register (rbs): the rbs contains the address in internal ram where the frame (start ing with the i - field) being received is to be stored. the cpu should write rbs only when the siu is not receiving a frame, rbe = 0. rbs is byte addressable. rbs bit: 7 6 5 4 3 2 1 0 rbs.7 rbs.6 rbs.5 rbs.4 rbs.3 rbs.2 rbs.1 rbs.0
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 31 of 49 1 - 888 - 824 - 4184 receive buffer le ngth register (rbl): the rbl contains the length, in number of bytes, of the i - field storage area in internal ram. rbl = 0 is valid (no i - field). the cpu should write rbl only when the siu is not receiving a frame, rbe = 0. the receive buffer will not wrap around after address 191 (bfh). a buffer end is automatically generated when address 191 is reached. rbl is byte addressable. rbl bit: 7 6 5 4 3 2 1 0 rbl.7 rbl.6 rbl.5 rbl.4 rbl.3 rbl.2 rbl.1 rbl.0 receive field length register (rfl): the rf l contains the length, in number of bytes, of the i - field of the frame received and stored in internal ram. rfl = 0 is valid (no i - field). the cpu should access rfl only when the siu is not receiving a frame, rbe = 0. rfl is loaded by the siu. rfl is byte addressable. rfl bit: 7 6 5 4 3 2 1 0 rfl.7 rfl.6 rfl.5 rfl.4 rfl.3 rfl.2 rfl.1 rfl.0 receive control byte register (rcb): the rcb contains the control field of the frame received and stored in internal ram. rcb is only readable by the cpu and the cpu should access rcb only when the siu is not receiving a frame, rbe = 0. rcb is loaded by the siu. rcb is byte addressable. rcb bit: 7 6 5 4 3 2 1 0 rcb.7 rcb.6 rcb.5 rcb.4 rcb.3 rcb.2 rcb.1 rcb.0 dma count register (dma cnt): the dma cnt re gister contains the number of bytes remaining for the information field currently being used. this register is an ice support register. dma cnt is byte addressable. dma cnt bit: 7 6 5 4 3 2 1 0 dma cnt.7 dma cnt.6 dma cnt.5 dma cnt.4 dma cnt.3 dma cnt .2 dma cnt.1 dma cnt.0
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 32 of 49 1 - 888 - 824 - 4184 dma count register (fifo): the fifo register is actually three registers that make a three byte fifo. these are used as temporary storage between the eight bit shift register and the receive buffer when an information field is received. this register is an ice support register. fifo is byte addressable. fifo bit: 7 6 5 4 3 2 1 0 fifo*.7 fifo*.6 fifo*.5 fifo*.4 fifo*.3 fifo*.2 fifo*.1 fifo*.0 * = 1, 2 or 3 for fifo1, fifo2, fifo3 respectively. siu state counter (siust) : the siust register indicates which state the siu state machine is currently in. this in turn indicates what task the siu is performing or which field is expected next by the siu. this register should not be written to. this register is an ice support register. siust is byte addressable. siust bit: 7 6 5 4 3 2 1 0 siust .7 siust .6 siust .5 siust .4 siust .3 siust .2 siust .1 siust .0
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 33 of 49 1 - 888 - 824 - 4184 data clocking options the siu may be clocked in one of two ways, with an external clock or in a self - clocked m ode. in the external clocked mode a serial clock must be provided on sclk. this clock must be synchronized to the serial data. incoming data is sampled at the rising edge of sclk. outgoing data is shifted out at the falling edge of sclk. in the self - clocked mode the siu uses a reference clock and the serial data to reproduce the serial data clock. the reference clock can be an external source applied to sclk, the ia8044/ia8344?s internal clock or the timer 1 overflow. the reference clock must be 16 x or 32x the data rate. a dpll uses the reference clock and the serial data to adjust the sample time to the center of the serial bit. it does this by adjusting from a serial data transition in increments of 1/16 of a bit time. the maximum data rate i n the externally clocked mode is 2.4mbps in a point - to - point configuration and 1.0mbps in a loop configuration. with a 12 mhz cpu clock the maximum data rate in the self - clocked mode with an external clock is 375kbps. the maximum data rate in the self - cl ocked mode with an internal clock will depend on the frequency of the ia8044/ia8344?s input clock. an ia8044/ia8344 using a 12mhz input clock can operate at a maximum data rate of 375kbps. the serial mode register bits 5, 6, and 7 select the clocking opt ion for the siu. (see smd register description) operational modes the siu operates in one of two modes, auto or flexible. the mode selected determines how much intervention is required by the cpu when receiving and transmitting frames. in both modes s hort frames, aborted frames, and frames with crc errors will be ignored. auto mode allows the siu to recognize and respond to specific sdlc frames without the cpus intervention. this provides for a faster turnaround time but restricts the operation of th e siu. when in auto mode the siu can only act as a normal response secondary station and responses will adhere to ibm?s sdlc definitions. when receiving in the auto mode the siu receives the frame and examines the control byte. it will then take the app ropriate action for that frame. if the frame is an information frame the siu will load the receive buffer, interrupt the cpu and make the required response to the primary station. the siu in auto mode can also respond to the following commands from the p rimary station. rr (receive ready), rnr (receive not ready), rej (reject), up (unnumbered poll) also called nsp (non - sequenced poll) or orp (optional response poll). in auto mode when the transmit buffer is full the siu can transmit an information frame when polled for information. after transmission the siu waits for acknowledgement from the receiving
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 34 of 49 1 - 888 - 824 - 4184 station. if the response is positive the siu interrupts the cpu. if the response is negative the siu retransmits the frame. the siu can send the follo wing responses to the primary station. rr (receive ready), rnr (receive not ready). the flexible mode requires the cpu to control the siu for both transmitting and receiving. this slows response time but allows full sdlc and limited hdlc compatibility a s well as variations. in flexible mode the siu can act as a primary station. the siu will interrupt the cpu after completion of a transmission without waiting for a positive acknowledgement from the receiving station. basic sdlc frame flag address contr ol information fcs flag ia 8x 44 frame parameters: flag - 8 bits address - 8 bits control - 8 bits information - n bytes (where n 192) fcs - 16 bits flag - 8 bits
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 35 of 49 1 - 888 - 824 - 4184 frame format options the various frame formats available with the ia8044/ia8344 are the standard sdlc format, the no control field format, the no control field and no address field format and the no fcs field format. the standard sdlc format consists of an opening flag, an 8 - bit address field, an 8 - bit control field, and n - byte inf ormation field, a 16 - bit frame check sequence field and a closing flag. the fcs is generated by the ccit - crc polynomial (x16 +x12 + x5 + 1). the fcs is calculated on the address, control and information fields. the address and control fields may not be extended. the address is contained in stad and the control filed is contained in either rcb or tcb. this format is supported by both auto and flexible modes. the no control field format is only supported by the flexible mode. in this format tcb and rcb are not used and the information field starts immediately after the address field. a control field may still be used in the frame but the siu will treat it as a byte of the information field. the no control field and no address field format is only supp orted by the flexible mode. in this format stad, tcb and rcb are not used and the information field starts immediately after the opening flag. this option can only be used with the no control field option. again a control field and address field may sti ll be used in the frame but the siu will treat each as a byte of the information field. the no fcs field format prevents an fcs from being generated during transmission or being checked during reception. this option may be used in conjunction with the ot her frame format options. this option will work with both flexible and auto modes. in auto mode it could cause protocol violations. an fcs field may still be used in the frame but the siu will treat it as a byte of the information field. all the possib le frame format combinations are shown in the table below along with the bit settings that select a given format.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 36 of 4 9 1 - 888 - 824 - 4184 frame format options frame option nfcs nb am frame format standard sdlc flexible mode 0 0 0 fl ad co inf fcs fl standard sdlc auto mode 0 0 1 fl ad co inf fcs fl no control field flexible mode 0 1 1 fl ad inf fcs fl no control field no address field flexible mode 0 1 0 fl inf fcs fl no fcs field flexible mode 1 0 0 fl ad co inf fl no fcs field auto mode 1 0 1 fl ad co inf fl no control field no fcs field flexible mode 1 1 1 fl ad inf fl no control field no address field no fcs field flexible mode 1 1 0 fl inf fl fl - > flag ad - > address field co - > control field inf - > information field fcs - > frame check sequence hd lc restrictions the ia8044/ia8344 supports a subset of the hdlc protocol. the differences include the restriction by the ia8044/ia8344 of the serial data to be in 8 - bit increments. in contrast hdlc allows for any number of bits in the information field. hdlc provides an unlimited address field and an extended frame number sequencing. hdlc does not support loop configuration. siu details the siu is composed of two functional blocks with each having several sub blocks. the two blocks are called the bit processor (bip) and the byte processor (byp).
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 37 of 49 1 - 888 - 824 - 4184 bit and byte processors bip the bip consists of the dpll, nrzi encoder/decoder, serial/parallel shifter, zero insertion/deletion, shutoff logic and fcs generation/checking. the nrzi logic compares the curr ent bit to the previous bit to determine if the bit should be inverted. the serial shifter converts the outgoing byte data to bit data and incoming bit data to byte data. the zero insert/delete circuitry inserts and deletes zeros and also detects flags(0 1111110), go - aheads (ga) (01111111) and aborts (1111111). the pattern 1111110 is detected as an early go - ahead that can be turned into a flag in loop configurations. the shutoff detector is a three bit counter that is used to detect a sequence of eight z eros, which is the shutoff command in loop mode transmissions. it is cleared whenever a one is detected. the fcs logic performs the generation and checking of the fcs value according to the polynomial described above. the fcs register is set to all 1?s prior to each calculation. if a crc error is generated on a receive frame the siu will not interrupt the cpu and the error will be cleared upon receiving an opening flag. byp the byp contains registers and controllers used to perform the manipulations re quired for sdlc communications. the byp registers may be accessed by the cpu (see sfr section above). the byp contains the siu state machine that controls transmission and reception of frames.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 38 of 49 1 - 888 - 824 - 4184 diagnostics a diagnostic mode is included with the ia8044/i a8344 to allow testing of the siu. diagnostics use port pins p3.0 and p3.1. writing a 0 to p3.1 enables the diagnostic mode. when p3.1 is cleared writing data to p3.0 has the effect of writing a serial data stream to the siu. p3.0 is the serial data an d any write to port 3 will clock sclk. the transmit data may be monitored on p3.1 with any write to port 3 again clocking sclk. in the test mode p3.0 and p3.1 pins are placed in the high impedance state. diagnostic signal routing
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 39 of 49 1 - 888 - 824 - 4184 ac/dc parameters absolute maximum ratings: ambient temperature under bias........................?.?..... - 40c to +85c storage temperature.......................................?........?..... - 40c to 150c power supply (v dd ).................... ...............?????.... - 0.3 to +6vdc voltage on any pin to vss...................................?..?.... - 0.3 to (v dd +0.3) - see note 1 power dissipation...................................................................2w dc characteristics symbol parameter min typ max unit vil input low voltage - - 0.8 v vih input high voltage 2.0 - - v vol output low voltage (iol= 4ma) - - 0.4 v voh output high voltage (ioh= 4ma) 3.5 - - v rpu pull-up resistance (ports 1,2,3) - 50 - kw rpd pull-down resistance (rst) - 50 - kw iil input low current (ports 1, 2, 3) -100 1 a iil1 input low current (all other inputs) -1 1 a iih input high current (rst) -1 - 100 a iih1 input high current (all other inputs) -1 1 a ioz tri-state leakage current (port 0,1,2,3) -10 10 a icc power supply current (@ 12 mhz) 50 ma cio pin capacitance - 4 - pf notes: 1. this device does not contain eprom or it?s related programming circuitry. therefore this limit must be adhered to especially for input pin ea that in the intel device is used as the programming voltage pin. exceeding the listed ma ximum voltage will cause damage to the device.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 40 of 49 1 - 888 - 824 - 4184 a.c. characteristics t a = - 40 c to +85 c, vdd = 5v 10%, vss = 0v, load capacitance = 87pf external program memory characteristics min max min max tlhll ale pulse width 171 2tclcl+4 ns tavll address valid to ale low 75 tclcl-8 ns tllax address hold after ale low 74 tclcl-9 ns tlliv ale low to valid instr. in. 298 4tclcl-35 ns tllpl ale low to psenn low 83 tclcl ns tplph psenn pulse width 254 3tclcl+4 ns tpliv psenn low to valid instr. in 215 3tclcl-35 ns tpxix input instr. hold after psenn 0 0 ns tpxiz input instr. float after psenn 76 tclcl-7 ns tpxav psenn to address valid 91 tclcl+8 ns taviv address to valid instr. in 373 5tclcl-43 ns tazpl address float to psenn -9 -9 ns tcy machine cycle 996 12tclcl ns unit variable clock 1/tclcl = 3.5 mhz to 12 mhz symbol parameter 12 mhz osc external data memory characteristics min max min max trlrh rdn pulse width 487 6tclcl-13 ns twlwh wrn pulse width 487 6tclcl-13 ns tllax address hold after ale 74 tclcl-9 ns trldv rdn low to valid data in. 383 5tclcl-35 ns trhdx data hold after rdn 0 0 ns trhdz data float after rdn 165 2tclcl-2 ns tlldv ale low to valid data in 633 8tclcl-34 ns tavdv address to valid data in. 708 9tclcl-42 ns tllwl ale low to rdn or wrn low 250 250 3tclcl 3tclcl ns tavwl address to rdn or wrn low 325 4tclcl-8 ns tqvwx data valid to wrn transistion 76 tclcl-7 ns tqvwh data setup before wrn high 563 7tclcl-20 ns twhqx data held after wrn 86 tclcl+3 ns trlaz rdn low to address float 9 9 ns twhlh rdn or wrn high to ale high 83 83 tclcl tclcl ns unit symbol parameter 12 mhz osc variable clock 1/tclcl = 3.5 mhz to 12 mhz
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 41 of 49 1 - 888 - 824 - 4184 serial interface characteristics symbol parameter min max unit tdcy data clock 420 ns tdcl data clock low 184 ns tdch data clock high 184 ns ttd transmit data delay 125 ns tdss data setup time 26 ns tdhs data hold time 58 ns external clock drive characteristics min max tclcl oscillator period 52 ns unit symbol parameter
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 42 of 49 1 - 888 - 824 - 4184 waveforms memory access program memory read cycle ale psenn port_0 port_2 instr. in a7-a0 instr. in a7-a0 instr. in instr. in address or sfr-p2 address a15-a8 address a15-a8 address a15-a8 tcy tlhll tlliv tllpl tplph tavll tpliv tazpl taviv tllax tpxav tpxiz tpxix data memory read cycle ale psenn rdn port_0 port_2 a7 - a0 data in address a15 - a8 or sfr - p2 address a15 - a8 or sfr - p2 twhlh trlrh tllwl tavwl tlldv tllax trldv trlaz trhdz trhdx tavdv
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 43 of 49 1 - 888 - 824 - 4184 data memory write cycle ale psenn wrn port_0 port_2 a7 - a0 data out data out address a15 - a8 or sfr - p2 address a15 - a8 or sfr - p2 tavwl tllax twlwh twhlh twhqx tllw l tqvwx tqvwh serial i/o waveforms synchronous data transmission sclk data tdcl ttd tdch tdcy synchronous data reception sclk data tdhs tdss tdch tdcl tdcy
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 44 of 49 1 - 888 - 824 - 4184 d d1 e e1 bottom view packaging information plcc package package dimensions for 44 lead plcc symbol typical (in inches) a 0.180 a1 0.110 d1 0.653 d2 0.610 d3 0.500 e1 0.653 e2 0.610 e3 0.500 e 0.050 d 0.690 e 0.690 d3 e3 pin 1 identifier & zone 0.045*45 o top view .004 .02 min. r 0.035 seating plane a1 e 0.026-0.032 a 0.013-0.021 d2 / e2 side view
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 45 of 49 1 - 888 - 824 - 4184 d l a1 a b b1 e side view (length) lead 1 identifier 1 lead count direction e1 e top pdip package package dimension s for 40 lead pdip (600 mil.) symbol typical (in inches) a 0.155 a1 0.010 b 0.018 b1 0.050 c 0.010 d 2.055 e 0.600 e1 0.545 e 0.100 eb 0.650 l 0.130 eb c side view (width)
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 46 of 49 1 - 888 - 824 - 4184 ordering information part number temperature grade ia8044 - pdw40i - 01 industrial ia8044 - p lc44i - 01 industrial ia8344 - pdw40i - 01 industrial ia8344 - plc44i - 01 industrial cross reference to original part numbers innovasic part number intel part number ia8044 - plc44i q n8044ah q n8044ah - r0117 ia8044 - pdw40i q p8044 q p8044ah q p8044ah - r0117 q tp 8044ah q tp8044ah - r0117 ia8344 - plc44i q n8344ah q tn8344ah ia8344 - pdw40i q p8344 q p8344ah q tp8344ah
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 47 of 49 1 - 888 - 824 - 4184 errata errata data listed for a particular version of the device apply only to that version. if errata data applies to more than one versi on it will be listed under each version affected. errata data that applies to all versions is listed under the heading ?version all?. innovasic devices are manufactured as prototypes and production units. prototype versions are denoted as ?pxx? and produ ction versions are denoted as ?xx? with xx being the version number (i.e. 03). version all : issue: cannot read internal rom with eprom verification method. solution: must use alternate method to read internal rom. the ia 8 x 44 does not contain internal e prom and therefore does not support the eprom read feature. issue: the ia8 x 44 has a different pullup value than the intel version. the intel version can source more current than the ia 8 x 44. solution: adjust external circuits if necessary. version p00 : issue: incorrect version of intel 8044 code in internal rom. internal rom contains version 2.1 it should contain version 2.3. solution: version 2.3 rom code must be run from external memory. future versions of device will contain version 2.3. issue: the jmp @a+dptr instruction incorrectly adds carry out of lower byte into higher byte of calculated pc value (was using carry as if the @a was a signed value, should be an absolute value). solution: avoid use of this instruction or modify code to account f or error. future versions of device will execute this instruction correctly. issue: when using edge sensitive interrupts the device may miss an interrupt. the problem occurs when enabling the interrupts or when tcon is being written to. solution: chang e to level sensitive interrupts or use external registers for int0/1. issue: reads from unused internal locations return 00h. when they should return ffh except for two locations which should return 00h. solution: avoid reading unused locations or mask th e value from unused locations. issue: setting ie0 or ie1 in tcon does not force an interrupt when in level sensitive mode. solution: use edge sensitive mode for these two interrupt sources.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 48 of 49 1 - 888 - 824 - 4184 issue: port2 buffer bits set high are not actively driven whe n executing a movx a,@ri or a movx @ri,a instruction. during these instructions any bit that was driven low by the previous value on port2 but is high in the port2 buffer will not reach a valid high level before ale goes low. solution: avoid the use of t hese instructions or add strong pullups (approximately 10k) to port2 externally. issue: race condition on transmit response in auto mode causes bad control byte to be transmitted.. solution: in firmware wait for rts=1 before telling transmit to start. issue: device does not sense the end of buffer during a receive. solution: no workaround available. issue: receiving continuous flags (7eh) while in loop mode will not allow a slave device to transmit. the device is only able to transmit when the line is idle. solution: do not send continuous flags. version 00/p01 : issue: the following registers change value after an external reset, stad, tbs, tbl, tcb, rbs, rbl, rfl, and rcb. these registers should retain there pre - reset values. solution: store re gister values in memory (internal or external) to be restored after reset. issue: device may miss external interrupts with narrow pulse widths when in edge sensitive mode and tight software loops that check tcon. solution: place nops in loop to allow tim e to capture interrupt.. issue: intermittent drop out in slave mode, followed by normal operation. dropouts can be caused by either noise on the reset pin or xtal1 being unconnected when using a clock source. solution: filter reset if necessary. ensure that xtal1 is tied low when using a clock source. issue: when used as a slave in loop mode the device may misinterpret a byte due to an internal bit counter error. this may cause the device to think it has seen a go - ahead and can transmit when it actua lly should not transmit. solution: no workaround available. issue: if the synchronous mode is used (external sclk is provided), gating off the sclk may cause the device to communicate erratically. depending on when the sclk is gated off the siu may not have finished its present task. when the sclk is restarted the device may not respond to communications. solution: do not gate off the external sclk.
ia8044/ia8344 data sheet sdlc communications controller copyright ? 2003 eng210010112 - 00 www.innovasic.com innov asic customer support: the end of obsolescence ? page 49 of 49 1 - 888 - 824 - 4184 issue: the chip does not operate properly, showing intermittent errors. difficulty with accessing exte rnal memory. the signals used to access external memory do not have the correct timing. solution: adjust signal timing externally if possible. issue: the device exhibits a 24mhz ripple on output pins. clock/osc switching causes noise to be induced ont o power rails. solution: no workaround available. issue: the chip fails when placed in emulators. ale and psen do not tristate during reset. solution: no workaround available.

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